EPM5032JC-20 vs EPM5032JC Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032JC-20 sa pamamagitan ng Altera at EPM5032JC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032JC-20 | EPM5032JC |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Family | MAX 5000 | MAX 5000 EPLD |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| Product Terms (P-terms) | 320 | — |
| Propagation Delay (tPD) | 20 ns | [DATA_NEEDED: specific speed grade value] |
| Maksimum na Taktiko ng Oras | 62.5 MHz | — |
| Setup Time | 10 ns | — |
| I/O Lines | 16 (bidirectional) | — |
| Dedicated Inputs | 8 | — |
| Total Inputs | 24 | — |
| Packhaging | 68-pin JLCC (windowed ceramic) | PLCC-44 |
| Process Technology | CMOS | — |
| Erase Method | UV (12V VPP + ultraviolet exposure) | — |
| Programming Voltage (VPP) | 12 V | — |
| Architecture | PAL-type AND-OR array with PIA interconnect | — |
| Katayuan ng Lifecycle | Obsolete (legacy Altera MAX 5000) | — |
| Logic Gates | — | 600 usable gates |
| Maximum I/O Pins | — | 40 |
| Supply Voltage (VCC) | — | 5 V |
| Input Type | — | TTL-compatible |
| Type ng Output | — | TTL/CMOS-compatible |
| Temperature na Operasyon | — | 0C to +70C (commercial) |
| Uri ng Pagpapasok | — | Surface Mount (J-lead) |
| Programmability | — | UV-erasable (windowed ceramic) / OTP variants |
| Design Software | — | MAX+PLUS II / Quartus legacy |
| JEDEC Standard | — | JEDEC PLCC-44 footprint |
| Tindminan RoHS | — | unknown |
| Lead-Free | — | unknown |