EPM5032PC-15 vs EPM5032PC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032PC-15 sa pamamagitan ng Altera at EPM5032PC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032PC-15 | EPM5032PC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 32 | — |
| Usable Gates | 600 | 600 |
| Logic Elements / LABs | 1 LAB (4 macrocells per group) | — |
| Propagation Delay (tPD) | 15 ns | 20 ns |
| Maximum Internal Frequency | 76.9 MHz (some sources list 83.3 MHz) | — |
| Operating Voltage (VCC) | 5 V (typ.) | — |
| Technology Node | 0.8 micron CMOS | — |
| Configuration Memory | UV-Erasable EPROM | — |
| Dedicated Inputs | 7 | 24 |
| Bidirectional I/O Pins | 16 | — |
| Total Array Inputs | 24 | — |
| Packhaging | 28-pin PDIP (PC suffix = windowed CerDIP) | PDIP-28 (Plastic DIP, 28-pin) |
| Pin/Package Suffix | PC = Windowed Ceramic DIP | — |
| Speed Grade | 15 (15 ns tPD) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Tool | Altera Logic Programmer + MAX+plus II | — |
| Tindminan RoHS | Non-compliant (CerDIP window, contains Be) | [DATA_NEEDED: RoHS status] |
| Lead-Free | No | — |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole |
| Programming Type | — | OTP (One-Time Programmable) |
| Macrocells | — | 32 |
| Logic Blocks | — | 2 Logic Array Blocks |
| Product Terms | — | 320 |
| Bidirectional I/O Lines | — | 16 |
| Maksimum na Taktiko ng Oras | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Technology | — | CMOS, 0.65 um process |
| Architecture | — | PAL-type macrocells with Programmable Interconnect Array (PIA) |