EPM5032SC-20 vs EPM5032JC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032SC-20 sa pamamagitan ng Altera at EPM5032JC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032SC-20 | EPM5032JC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | 8 |
| I/O Pins | 16 | — |
| Outputs | 16 | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Speed Grade | -20 (20 ns) | — |
| Architecture | PAL-type, CMOS, UV-erasable | PAL-type AND-OR array with PIA interconnect |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Packhaging | 20-pin SOIC (Small Outline) | 68-pin JLCC (windowed ceramic) |
| Temperature na Operasyon | 0 °C to +70 °C (commercial grade) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC typical range] | — |
| Technology | CMOS EPROM cell | — |
| Programmability | One-time programmable (windowless SOIC) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status not confirmed in verified data] | — |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | — | 1 |
| Product Terms (P-terms) | — | 320 |
| Maksimum na Taktiko ng Oras | — | 62.5 MHz |
| Setup Time | — | 10 ns |
| I/O Lines | — | 16 (bidirectional) |
| Total Inputs | — | 24 |
| Process Technology | — | CMOS |
| Erase Method | — | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | — | 12 V |
| Katayuan ng Lifecycle | — | Obsolete (legacy Altera MAX 5000) |