EPM5064JC vs EPM5064LC Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5064JC sa pamamagitan ng Altera at EPM5064LC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5064JC EPM5064LC
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable PLD) CPLD (Complex Programmable Logic Device)
Macrocells 64 —
Usable Gates 1,250 (approx.) 1.25K
Logic Array Inputs 36 —
Logic Array Outputs 64 —
Packhaging 68-pin PLCC (JEDEC) PLCC-44 (LCC-44, J-lead)
Uri ng Pagpapasok Surface Mount (socketed) Surface Mount
Supply Voltage (VCC) 5 V (typical, 4.75 V - 5.25 V range) 4.75 V to 5.25 V
I/O Logic Level TTL / CMOS compatible —
Configuration Memory EPROM (UV-erasable window or OTP) —
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] 0C to +70C (Commercial)
Pin-to-Pin Delay (tPD) [DATA_NEEDED: specific tPD grade value] —
Maximum Frequency (fMAX) [DATA_NEEDED: fCNT grade value] —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status - pre-RoHS legacy part, likely non_compliant]
Lead-Free [DATA_NEEDED: lead-free status] —
Level ng MSL [DATA_NEEDED: MSL rating] —
Programming Tool Altera MAX+PLUS II / Quartus II (legacy device support) —
Programming Type — OTP (One-Time-Programmable, UV-erasable EPROM)
Macro Cells — 64
Logic Array Blocks (LABs) — 4
Propagation Delay (tPD) — 55 ns
Total Inputs — 36 (7 dedicated + 29 I/O)
I/O Pins — 28 bidirectional + 4 dedicated input
Process Technology — CMOS EPROM
Lead Free — [DATA_NEEDED: lead-free status]

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