EPM5128GC vs EPM5064JC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128GC sa pamamagitan ng Altera at EPM5064JC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5128GC EPM5064JC-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Macrocells 128 64
Usable Gates 2,500 1250
Logic Elements / LABs [DATA_NEEDED: LAB count] —
User I/Os 68 —
Package Type WPGA (Windowed Ceramic Pin Grid Array) —
Package Code WPGA —
Number of Terminals 68 —
Terminal Form PIN/PEG (through-hole PGA with alignment pegs) —
Package Shape Square —
Temperature Grade Commercial —
Supply Voltage (Vcc) 5 V —
Process Technology CMOS, UV-erasable —
Architecture EPLD, programmable AND/OR array with fixed OR plane —
Propagation Delay (tpd) [DATA_NEEDED: tpd in ns] —
Maximum Frequency (fmax) [DATA_NEEDED: fmax in MHz] —
Programmable Security Bit Yes —
Configuration Memory Non-volatile UV-EPROM (windowed ceramic) —
Uri ng Pagpapasok Through-Hole (PGA socket required) —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] —
Logic Array Blocks (LABs) — 4
Propagation Delay (tPD) — 45 ns
Maximum Clock Frequency (fMAX) — 50 MHz
Dedicated Inputs — 7
I/O Pins — 28
Interconnect — Programmable Interconnect Array (PIA)
Technology — CMOS, UV-erasable EPROM
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Programming Method — UV-erase + EPROM programmer (not ISP)
Packhaging — 28-pin CLCC (J-lead, ceramic, windowed)
Temperature na Operasyon — [DATA_NEEDED: commercial or industrial grade]
Compliance — RoHS status unknown (ceramic/J-lead windowed part, legacy product)

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