EPM5192AJC84-20 vs EPM5192AJC84-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192AJC84-20 sa pamamagitan ng Altera at EPM5192AJC84-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 ObsoleteAltera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 ObsoletePagsanggunian na paghahambing
| Parametro | EPM5192AJC84-20 | EPM5192AJC84-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable/OTP Complex PLD (CPLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 33 ns (speed grade -20) | 15 ns |
| Maksimum na Taktiko ng Oras | 66.7 MHz | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V | — |
| Dedicated Inputs | 7 | — |
| User I/O Lines | 64 | — |
| Process Technology | CMOS, UV-erasable EEPROM | CMOS EPROM |
| Packhaging | 84-pin PLCC J-Lead (WQCCJ, J84) | 84-pin PLCC (J84C) windowed ceramic |
| Operating Temperature Grade | Commercial | — |
| Uri ng Pagpapasok | Surface Mount (J-Lead) | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (contains Pb, ceramic windowed package) |
| Programming Tool | Altera MAX+PLUS II / Quartus (legacy) | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Maximum Clock Frequency (fMAX) | — | 83.3 MHz |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Technology | — | CMOS, UV-erasable EPROM |
| Temperature na Operasyon | — | [DATA_NEEDED: commercial/industrial/military grade] |
| Programming Method | — | UV-erase + EPROM programming (windowed package) |
| Logic Blocks | — | 16 Logic Array Blocks (LABs) |
| I/O Pins | — | [DATA_NEEDED: user I/O count] |