EPM5192JC-1 vs EPM5192GC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC-1 sa pamamagitan ng Altera at EPM5192GC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192JC-1 | EPM5192GC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 (Classic) |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Technology | CMOS, UV-Erasable / OTP | — |
| Macrocells | 192 | 192 |
| Usable Gates | 3750 | 3,750 |
| Propagation Delay (tPD) | 40 ns (speed grade -1) | — |
| Maximum Internal Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| User I/O Pins | 84 | 64 |
| Package Type | 84-pin Ceramic Quad Flat Pack (CQFP), windowed | — |
| JEDEC Package Code | S-CQCC-J84 | — |
| Temperature na Operasyon | 0 C to +70 C (commercial) | [DATA_NEEDED: operating temperature grade] |
| Configuration Memory | UV-EPROM (erasable under UV lamp) | — |
| Programming Interface | Altera MAX programming interface (parallel, pre-JTAG for this family) | — |
| Process | CMOS EPROM | — |
| I/O Standard | TTL/CMOS 5 V compatible | — |
| Logic Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 12 |
| Dedicated Inputs | — | 7 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Frequency (fMAX) | — | 62.5 MHz |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Packhaging | — | 100-pin Ceramic PGA (GC) |
| Uri ng Pagpapasok | — | Through-Hole (PGA) |
| Configuration Method | — | UV-Erase / One-Time Programmable |
| Interconnect | — | Peripheral Interconnect Array (PIA) |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |