EPM5192JC-1N vs EPM5192JC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC-1N sa pamamagitan ng Altera at EPM5192JC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192JC-1N | EPM5192JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD - Complex Programmable Logic Device |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Usable Gates | 3750 | 3750 |
| User I/O Pins | 64 | 84 |
| Dedicated Inputs | 7 | — |
| External Clock Inputs (GCLK) | 1 | — |
| Propagation Delay (tPD) | 40 ns | 40 ns (speed grade -1) |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Technology | CMOS EPROM (UV-erasable) | CMOS, UV-Erasable / OTP |
| Packhaging | 84-pin Ceramic Quad Flat Pack (CQFP) | — |
| JEDEC Package Code | S-CQCC-J84 | S-CQCC-J84 |
| Temperature na Operasyon | [DATA_NEEDED: industrial/commercial temperature range] | 0 C to +70 C (commercial) |
| Programming Interface | JTAG / Altera ByteBlaster | Altera MAX programming interface (parallel, pre-JTAG for this family) |
| Maximum Internal Frequency (fMAX) | — | 62.5 MHz |
| Package Type | — | 84-pin Ceramic Quad Flat Pack (CQFP), windowed |
| Configuration Memory | — | UV-EPROM (erasable under UV lamp) |
| Process | — | CMOS EPROM |
| I/O Standard | — | TTL/CMOS 5 V compatible |