EPM5192JC1 vs EPM5192JC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC1 sa pamamagitan ng Intel at EPM5192JC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JC1 EPM5192JC-2
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 (MAX 5xxx CPLD) —
Manufacturer Intel (formerly Altera Corporation) —
Macro Cells 192 —
Usable Gates 3750 —
Maximum Operating Frequency 62.5 MHz —
Supply Voltage (VCC) 5 V (nominal) —
Process Technology 0.5 µm CMOS, UV-erasable EPROM CMOS
Propagation Delay (typ) [DATA_NEEDED: propagation delay in ns] —
I/O Pins [DATA_NEEDED: I/O pin count] —
Packhaging [DATA_NEEDED: exact package from datasheet] 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed)
Uri ng Pagpapasok [DATA_NEEDED: surface mount or through-hole] Surface Mount
Temperature na Operasyon [DATA_NEEDED: operating temp range] —
Programming Interface JTAG-compatible (Altera MAX 5xxx) —
Logic Blocks (LABs) 24 (8 macrocells per LAB) —
Tindminan RoHS unknown [DATA_NEEDED: RoHS compliance]
AEC-Q100 not_applicable —
Lifecycle Obsolete - last-time-buy stock only at franchised distributors —
Device Family — MAX 5000
Product Type — UV-erasable Programmable Logic Device (PLD)
Macrocells — 192
Logic Array Blocks (LABs) — 12
Interconnect — Programmable Interconnect Array (PIA)
User I/O Pins — 64
Dedicated Inputs — 7
External Clock Inputs — 1
Propagation Delay (tPD) — 45 ns
Maksimum na Taktiko ng Oras — 40 MHz
Number of Terminals — 84
Programming Method — UV-erase / EPROM
Hanay ng Temperature na Operasyon — [DATA_NEEDED: operating temperature range]

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