EPM5192JC2 vs EPM5192JC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC2 sa pamamagitan ng Intel at EPM5192JC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192JC2 | EPM5192JC-1 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Usable Gates (equivalent) | 6000 | — |
| Maximum User I/O | 64 | — |
| Dedicated Inputs | 7 | — |
| External Clock Inputs | 1 (with shared input/clock capability) | — |
| Maksimum na Taktiko ng Oras | 50 MHz | — |
| Propagation Delay (tPD) | 45 ns (speed grade -2) | 40 ns (speed grade -1) |
| Process Technology | CMOS, UV-erasable | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Packhaging | PLCC-68 (JC) | — |
| Uri ng Pagpapasok | Surface Mount (socketable PLCC) | — |
| Programming | Altera Master Programmer / ByteBlaster via JTAG-style interface | — |
| Technology | — | CMOS, UV-Erasable / OTP |
| Usable Gates | — | 3750 |
| Maximum Internal Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| User I/O Pins | — | 84 |
| Package Type | — | 84-pin Ceramic Quad Flat Pack (CQFP), windowed |
| JEDEC Package Code | — | S-CQCC-J84 |
| Temperature na Operasyon | — | 0 C to +70 C (commercial) |
| Configuration Memory | — | UV-EPROM (erasable under UV lamp) |
| Programming Interface | — | Altera MAX programming interface (parallel, pre-JTAG for this family) |
| Process | — | CMOS EPROM |
| I/O Standard | — | TTL/CMOS 5 V compatible |