EPM5192LC-2N vs EPM5192LC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC-2N sa pamamagitan ng Altera at EPM5192LC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192LC-2N | EPM5192LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Flip-Flops | 192 | — |
| Logic Elements | 192 macrocells (PAL/GAL-style AND-OR array) | — |
| Package Type | LC (ceramic J-leaded, windowed UV-erasable package family) | LDCC (Leaded Ceramic Chip Carrier), plastic windowless |
| Speed Grade | -2 (tPD approximately 25 ns) | -1 |
| Propagation Delay (typical) | 25 ns | — |
| Volte ng Pagbibigay | 5 V (typical) | 5 V nominal (4.75 V to 5.25 V) |
| Programmability | UV-erasable EPROM cell | — |
| Uri ng Pagpapasok | Surface Mount (LC package) | — |
| Temperature na Operasyon | Commercial (0C to +70C) - inferred from speed-grade -2 designation | 0C to +70C (commercial) |
| Tindminan RoHS | Compliant (per -N lead-free suffix) | Non-compliant (ceramic LDCC with Pb-bearing terminations) |
| Lead-Free | Yes (per -N suffix) | — |
| Architecture | Programmable Logic Array (PLA) with global PIA | — |
| Programming Interface | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) | — |
| Device Type | — | EPLD / CPLD |
| Logic Gates | — | 3750 (typical usable) |
| Dedicated Inputs | — | 7 |
| User I/O | — | 64 |
| Bilang ng Pins | — | 84 |
| Propagation Delay | — | 25 ns |
| Maksimum na Taktiko ng Oras | — | 50 MHz |
| Technology | — | CMOS, UV-erasable / OTP EPROM cell |
| Programmable Memory | — | EPROM (one-time or UV-erasable) |