EPM5192LC vs EPM5192LC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC sa pamamagitan ng Altera at EPM5192LC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192LC EPM5192LC-25
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 7000S MAX 5000
Macrocells 192 192
Logic Array Blocks (LABs) 12 —
User I/O Pins 64 —
Dedicated Inputs 7 —
Global Clock Inputs 1 —
Propagation Delay (tPD) 55 ns (typical, commercial) —
Maximum Clock Frequency (fMAX) 50 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (nominal 5 V) —
Process Technology CMOS, UV-erasable/OTP EPROM configuration —
Programmable Interconnect Programmable Interconnect Array (PIA), fixed delay —
Boundary-Scan Support JTAG IEEE 1149.1 —
Programming Interface JTAG (ByteBlaster-compatible) JTAG / Altera programming hardware (legacy)
Operating Temperature (commercial) 0C to +70C —
Packhaging JLCC-68 (windowed ceramic, LC suffix) JLCC-84 (ceramic J-lead chip carrier)
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS status] Unknown (legacy ceramic package typically non-RoHS)
Product Type — CPLD (Complex Programmable Logic Device)
Logic Elements — 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture)
Pin-to-Pin Delay (tPD) — 25 ns
Speed Grade — -25 (25 ns)
Programmable Technology — UV-erasable / OTP (EPROM-based)
Temperature na Operasyon — 0C to +70C (commercial)
Volte ng Pagbibigay — 5 V (typical, MAX 5000)
I/O Standard — TTL-compatible
Configuration Memory — Non-volatile EPROM (on-chip)
Manufacturer — Altera Corporation (now Intel PSG)

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