EPM5192LC84-1 vs EPM5192GC84-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC84-1 sa pamamagitan ng Altera at EPM5192GC84-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192LC84-1 | EPM5192GC84-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable / OTP Complex PLD) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 7,500 | — |
| Speed Grade | -1 | — |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD ns value] | 40 ns (speed grade -1) |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Program Memory Type | UV-EPROM / OTP | — |
| Packhaging | 84-pin PLCC (LC84) | 84-pin PGA (Pin Grid Array), WPGA code |
| Uri ng Pagpapasok | Surface Mount (J-lead) | Through-hole (PGA socket) |
| Temperature na Operasyon | 0C to +70C (commercial) | — |
| I/O Count | [DATA_NEEDED: I/O pin count] | — |
| Tindminan RoHS | [DATA_NEEDED: not stated in provided data] | Compliant (per third-party distributor listing) |
| Process Technology | CMOS EPROM | — |
| Product Type | — | UV-Erasable/OTP Complex PLD (CPLD) |
| Technology | — | CMOS (EPROM-cell based) |
| Maksimum na Taktiko ng Oras | — | 50 MHz |
| Dedicated Inputs | — | 7 |
| User I/O Pins | — | 64 |
| Total Inputs / Outputs | — | 72 inputs / 64 outputs |
| Architecture | — | Shared input/clock and shared product terms |
| Temperature Grade | — | Commercial |
| Programming Method | — | UV erasure (quartz window) + EPROM programmer |
| Logic Element Type | — | Macrocells with AND/OR array |