EPM5192LI84 vs EPM5192ALI84-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LI84 sa pamamagitan ng Altera at EPM5192ALI84-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192LI84 | EPM5192ALI84-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | MAX 5000 |
| Product Type | UV-Erasable/OTP Complex PLD (CPLD) | UV-Erasable / OTP Complex PLD |
| Usable Gates | 3,750 gates | — |
| Macro Cells | 192 | — |
| Maximum Toggle Frequency | 40 MHz | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| User I/O Pins | 64 (max) | — |
| Hanay ng Temperature na Operasyon | -40 °C to +85 °C (industrial) | [DATA_NEEDED: temperature range] |
| Package Type | 84-pin PLCC (J-lead, package code J84/QCCJ) | — |
| Uri ng Pagpapasok | Surface Mount (socket-compatible) | Surface Mount (PLCC socket compatible) |
| Configuration Memory | OTP / UV-erasable EPROM | — |
| Programming Method | Stand-alone programmer (no JTAG on LI84 OTP variant) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Logic Compatibility | TTL-compatible I/O | — |
| Logic Macrocells | — | 192 |
| Dedicated Inputs | — | 7 |
| Bidirectional I/O Pins | — | 64 |
| Maximum Total Inputs | — | 72 |
| Propagation Delay (tPD) | — | 25 ns (-15 speed grade) |
| Process Technology | — | CMOS, non-volatile EPROM/OTP |
| Programmability | — | One-Time Programmable (windowless) |
| Packhaging | — | 84-pin PQCC (PLCC, J-Lead) |
| JEDEC JESD-30 Code | — | S-PQCC-J84 |
| Terminal Form | — | J Bend (J-Lead) |
| Operating Temperature Grade | — | Industrial |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC range] |