EPM570F100A5N vs EPM570F100C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570F100A5N sa pamamagitan ng Altera at EPM570F100C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570F100A5N | EPM570F100C4N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | MAX II |
| Logic Elements | 570 | 440 LE |
| Macrocells | 440 | 440 |
| User Flash Memory | 8 Kbits | 4.4 Kbits |
| Pin-to-Pin Delay (tPD) | 5.4 ns | — |
| Maximum Operating Frequency | 201.1 MHz | — |
| User I/O Pins (max) | 76 | — |
| Global Clock Lines | 4 | — |
| Supply Voltage - Core | 3.3 V | — |
| Supply Voltage - I/O Banks | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Process Technology | 0.18 µm flash | — |
| Packhaging | 100-ball FBGA | 100-FBGA (FineLine BGA) 11 mm x 11 mm |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| Temperature na Operasyon | 0°C to +85°C (commercial) | 0 C to +85 C (commercial) |
| Tindminan RoHS | Compliant | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O | — | 80 |
| Pin-to-Pin Delay (tPD1) | — | 5.4 ns |
| Configuration Technology | — | Flash (non-volatile, instant-on) |
| Operating Voltage (Core) | — | 3.3 V (internal regulator) |
| I/O Voltage Support (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Hot Socketing | — | Yes |