EPM570F100A5N vs EPM570F100I5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570F100A5N sa pamamagitan ng Altera at EPM570F100I5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570F100A5N | EPM570F100I5N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | MAX II |
| Logic Elements | 570 | — |
| Macrocells | 440 | 440 |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Pin-to-Pin Delay (tPD) | 5.4 ns | — |
| Maximum Operating Frequency | 201.1 MHz | 304 MHz |
| User I/O Pins (max) | 76 | — |
| Global Clock Lines | 4 | — |
| Supply Voltage - Core | 3.3 V | — |
| Supply Voltage - I/O Banks | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Process Technology | 0.18 µm flash | CMOS, Flash configuration cell |
| Packhaging | 100-ball FBGA | 100-ball FineLine BGA (11x11 mm) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1), in-system programmable |
| Temperature na Operasyon | 0°C to +85°C (commercial) | -40C to +100C (Industrial) |
| Tindminan RoHS | Compliant | Compliant |
| Device Type | — | CPLD (Flash-based) |
| Logic Elements (LEs) | — | 570 |
| Maximum User I/Os | — | 76 |
| Propagation Delay (tPD) | — | 8.7 ns (max), 5.4 ns (typical) |
| Supply Voltage (VCCINT) | — | 2.375 V to 3.6 V |
| Typical Supply Current (ICC) | — | 55 mA |
| I/O Standards Supported | — | LVCMOS, LVTTL, LVDS, SSTL, HSTL (1.5/1.8/2.5/3.3 V) |
| Global Clocks | — | 4 |
| Uri ng Pagpapasok | — | Surface Mount |
| Hot Socketing | — | Supported |