EPM570GF100I5N vs EPM570F100A5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570GF100I5N sa pamamagitan ng Intel at EPM570F100A5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570GF100I5N | EPM570F100A5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX II | — |
| Family | Complex Programmable Logic Device (CPLD) | MAX II |
| Logic Elements (LEs) | 570 | — |
| Macrocells | 440 | 440 |
| User I/Os | 76 | — |
| User Flash Memory (UFM) | 8192 bits | — |
| Propagation Delay (tPD) | 5.4 ns | — |
| Maximum Internal Frequency | 201.1 MHz | — |
| Supply Voltage VCCINT | 1.71 V to 1.89 V (typ 1.8 V) | — |
| I/O Bank Voltage VCCIO | 1.5 V / 1.8 V / 2.5 V / 3.3 V compatible | — |
| Process Technology | 0.18 µm CMOS Flash | 0.18 µm flash |
| Packhaging | FBGA-100 (11 x 11 mm, 1.0 mm pitch) | 100-ball FBGA |
| Uri ng Pagpapasok | Surface Mount | — |
| Temperature na Operasyon | -40 °C to +100 °C (Industrial) | 0°C to +85°C (commercial) |
| Programming Interface | JTAG (IEEE 1149.1) / ByteBlaster | JTAG (IEEE 1149.1) / ISP |
| Tindminan RoHS | Compliant | Compliant |
| Logic Elements | — | 570 |
| User Flash Memory | — | 8 Kbits |
| Pin-to-Pin Delay (tPD) | — | 5.4 ns |
| Maximum Operating Frequency | — | 201.1 MHz |
| User I/O Pins (max) | — | 76 |
| Global Clock Lines | — | 4 |
| Supply Voltage - Core | — | 3.3 V |
| Supply Voltage - I/O Banks | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |