EPM570GF100I5N vs EPM570GF100C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570GF100I5N sa pamamagitan ng Intel at EPM570GF100C5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570GF100I5N | EPM570GF100C5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX II | — |
| Family | Complex Programmable Logic Device (CPLD) | — |
| Logic Elements (LEs) | 570 | — |
| Macrocells | 440 | 440 |
| User I/Os | 76 | 76 |
| User Flash Memory (UFM) | 8192 bits | — |
| Propagation Delay (tPD) | 5.4 ns | 5.4 ns |
| Maximum Internal Frequency | 201.1 MHz | — |
| Supply Voltage VCCINT | 1.71 V to 1.89 V (typ 1.8 V) | — |
| I/O Bank Voltage VCCIO | 1.5 V / 1.8 V / 2.5 V / 3.3 V compatible | — |
| Process Technology | 0.18 µm CMOS Flash | — |
| Packhaging | FBGA-100 (11 x 11 mm, 1.0 mm pitch) | 100-LBGA (FBGA-100), 11 x 11 mm, 1.0 mm pitch |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40 °C to +100 °C (Industrial) | -40C to +125C (industrial) |
| Programming Interface | JTAG (IEEE 1149.1) / ByteBlaster | IEEE 1532 / JTAG (IEEE 1149.1) ISP |
| Tindminan RoHS | Compliant | Compliant (lead-free) |
| Device Family | — | MAX II |
| Logic Elements | — | 570 |
| Configuration Memory | — | On-chip Flash (non-volatile) |
| Core Voltage | — | 1.8 V (internal) |
| I/O Voltage Support | — | 1.8 V / 2.5 V / 3.3 V (5.0 V tolerant inputs) |
| Logic Family / Process | — | CMOS, Flash-based LUT |
| LABs | — | 4 (16 macrocells per LAB) |