EPM570GT100I5N vs EPM570T10015 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570GT100I5N sa pamamagitan ng Altera at EPM570T10015 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM570GT100I5N - 440-Macrocell CPLD, 5.4ns, MAX II, 100-TQFP | Altera
EPM570GT100I5N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM570GT100I5N | EPM570T10015 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | — |
| Logic Elements | 570 LE | 570 |
| Equivalent Macrocells | 440 macrocells | — |
| Number of LABs | 57 | — |
| User I/Os | 76 | — |
| Maximum Operating Frequency | 304 MHz | — |
| Propagation Delay (tPD1) | 5.4 ns | — |
| Operating Supply Voltage (Core) | 1.8 V | — |
| User Flash Memory | 8 Kbit | 8 Kbits |
| Packhaging | 100-pin TQFP (GT100) | TQFP-100 (T100) 14 x 14 mm |
| Uri ng Pagpapasok | Surface Mount (SMD/SMT) | — |
| Temperature na Operasyon | -40 °C to +100 °C (Industrial) | — |
| Process | 0.18 µm, 6-layer-metal flash | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| MultiVolt I/O Support | 1.8 V / 2.5 V / 3.3 V | — |
| Internal Oscillator | Yes | — |
| Non-volatile Configuration | Yes (instant-on, no external boot PROM) | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Device Family | — | MAX II |
| Macro Cells | — | 440 |
| Maximum User I/O Pins | — | 76 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (commercial/industrial speed grade) |
| Propagation Delay | — | [DATA_NEEDED: detailed tPD/tCO/tSU datasheet values] |
| Supply Voltage - Core (VCCINT) | — | 3.3 V (2.5 V variants exist in MAX II family) |
| Supply Voltage - I/O (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-volt I/O) |
| Hanay ng Temperature na Operasyon | — | -40 °C to +85 °C (industrial) |
| Configuration Memory | — | On-chip flash (non-volatile, instant-on) |
| Programming Interface | — | JTAG (IEEE 1149.1 / IEEE Std 1532) |
| Supported I/O Standards | — | LVTTL, LVCMOS, PCI, SSTL (per pin) |
| Process Technology | — | 0.18 µm |
| Level ng MSL | — | [DATA_NEEDED: moisture sensitivity level] |