EPM570T100C5 vs EPM570T100C4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570T100C5 sa pamamagitan ng Intel at EPM570T100C4 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM570T100C4 - 570 LEs, 5.4ns CPLD | Intel (Altera) MAX II | TQFP-100
EPM570T100C4 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM570T100C5 | EPM570T100C4 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX II | — |
| Family | MAX II CPLD | MAX II |
| Logic Elements | 570 | — |
| Macrocells | 440 | 440 |
| Maximum User I/O Pins | 76 | — |
| Propagation Delay (tpd) | 5.4 ns (max) | — |
| Maximum Frequency | 201.1 MHz | — |
| Process Technology | 0.18 µm | — |
| Internal Supply Voltage | 2.5 V / 3.3 V | — |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Packhaging | TQFP-100 (14x14 mm) | TQFP-100 (T100), 14 x 14 mm |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0°C to 85°C (TJ) | 0C to +85C (commercial) |
| Programming Interface | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) - ISP |
| Tindminan RoHS | Compliant | Compliant |
| Logic Elements (LEs) | — | 570 |
| Maximum User I/O Pins (this package) | — | 80 |
| Pin-to-Pin Propagation Delay (tPD) | — | 5.4 ns |
| General-Purpose SRAM | — | 4.4 Mbits |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Level ng MSL | — | [DATA_NEEDED: MSL Level] |
| On-chip Oscillator | — | Yes (3.3 MHz / 5.5 MHz selectable) |
| Internal Logic Analyzers / ISP | — | JTAG-based in-system programmable, no external boot PROM required |