EPM570T100C5N vs EPM240T100A5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570T100C5N sa pamamagitan ng Intel at EPM240T100A5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM240T100A5N - 192-Macrocell MAX II CPLD, 100-TQFP | Intel / Altera
EPM240T100A5N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM570T100C5N | EPM240T100A5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX II | — |
| Family | CPLD - MAX II | MAX II |
| Logic Elements (LE) | 570 | 240 |
| Macrocells | 440 | — |
| User I/Os | 76 | — |
| User Flash Memory | 8 Kbit | — |
| Process Technology | 0.18 µm 6-layer-metal Flash | 0.18 µm |
| Internal Performance | 201.1 MHz | — |
| Volte ng Pagbibigay | 2.5 V / 3.3 V | 2.5 V / 3.3 V |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | 0C to +85C (commercial, "A5N" suffix) |
| Packhaging | 100-pin TQFP (T100) | 100-pin TQFP (14 x 14 x 1.0 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) / ISP |
| I/O Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V MultiVolt | — |
| Tindminan RoHS | Compliant | Compliant (Pb-free) |
| Macro Cells | — | 192 |
| User I/O Count | — | 80 |
| Pin-to-Pin Logic Delay (tPD) | — | 4.7 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| I/O Bank Count | — | 4 (multi-voltage) |
| Configuration Memory | — | On-chip Flash (instant-on) |