EPM570T100I5N vs EPM570T100A5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570T100I5N sa pamamagitan ng Intel at EPM570T100A5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570T100I5N | EPM570T100A5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX II | — |
| Family | EPM570 | — |
| Logic Elements | 570 | 570 |
| Macrocells | 440 | 440 |
| User I/Os (max) | 76 | — |
| User Flash Memory | 8 Kbit | — |
| Packhaging | TQFP-100 (T100) | 100-pin TQFP |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Operating Supply Voltage (Core) | 2.5 V / 3.3 V | — |
| I/O Standards Supported | 1.5 V, 1.8 V, 2.5 V, 3.3 V (MultiVolt) | — |
| Programmable via JTAG | Yes (IEEE 1149.1) | — |
| In-System Programmable | Yes | — |
| Configuration Memory | Internal non-volatile Flash | On-chip non-volatile flash |
| Operating Temperature (Industrial) | -40C to +100C (junction) | — |
| Tindminan RoHS | Compliant | Compliant |
| Device Family | — | MAX II |
| User I/O Pins | — | 76 |
| Number of Logic Array Blocks (LABs) | — | 57 |
| Pin-to-Pin Logic Delay (tPD) | — | 5.4 ns |
| Maximum Internal Frequency | — | 304 MHz |
| Core Supply Voltage (VCCINT) | — | 1.8 V (typical) |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| User Flash Memory (UFM) | — | 8 Kbits |
| Programming Interface | — | JTAG (IEEE 1149.1) - ISP |
| Temperature na Operasyon | — | -40 °C to +125 °C (industrial) |