EPM570T144I5 vs EPM570T144C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570T144I5 sa pamamagitan ng Altera at EPM570T144C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570T144I5 | EPM570T144C5N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX II | MAX II |
| Macrocells (Logic Elements) | 440 | — |
| User I/O | 116 | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Pin-to-Pin Delay (tPD1) | 5.4 ns | — |
| Maximum Frequency (fMAX) | 304 MHz | 201.1 MHz |
| Supply Voltage - Core | 1.8 V | — |
| Supply Voltage - I/O Banks | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Packhaging / Kaso | TQFP-144 (144-LQFP, 20 x 20 mm) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40 °C to +100 °C (industrial) | 0 °C to +85 °C (commercial, C5 grade) |
| Process Technology | 0.18 µm flash | 0.18 µm 6-layer-metal flash |
| Programming Interface | JTAG (IEEE 1149.1) | IEEE 1149.1 JTAG (in-system programmable) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Series | — | MAX II Device |
| Logic Elements (LEs) | — | 570 |
| Macrocells | — | 440 |
| User I/Os | — | 116 |
| Internal User Flash Memory | — | 8 Kbit |
| Global Clocks | — | 4 |
| Core Voltage (VCCINT) | — | 1.8 V (typical, internally regulated) |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage, per bank) |
| Maximum User I/O Pins | — | 116 |
| Propagation Delay (tPD) | — | 5.5 ns (typical, [DATA_NEEDED: exact speed grade]) |
| Packhaging | — | TQFP-144 (20 × 20 mm, 0.5 mm pitch) |
| Configuration Storage | — | On-chip non-volatile flash |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI, LVDS, SSTL (per bank VCCIO) |
| Lead-Free | — | Yes |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |
| Design Software | — | Intel Quartus II (MAX II device support) |