EPM570ZM144C6N vs EPM570T144C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570ZM144C6N sa pamamagitan ng Altera at EPM570T144C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570ZM144C6N | EPM570T144C5N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Manufacturer | Intel (formerly Altera) | — |
| Family | MAX II | MAX II |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Logic Elements | 570 LEs (440 equivalent macrocells) | — |
| User I/Os | 76 (in 144-MBGA package) | 116 |
| Maximum Internal Frequency | 184.1 MHz | — |
| Core Voltage | 1.8 V | — |
| I/O Voltage Support | 1.5 V, 1.8 V, 2.5 V, 3.3 V (MultiVolt) | — |
| Process Technology | 0.18 µm 6-layer-metal flash | 0.18 µm 6-layer-metal flash |
| User Flash Memory (UFM) | 8 Kbits | — |
| Programmability | In-system programmable via JTAG (ISP) | — |
| Configuration Memory | Non-volatile flash | — |
| Packhaging | 144-ball Micro FBGA (ZM144), 6 x 6 mm, 0.5 mm pitch | TQFP-144 (20 × 20 mm, 0.5 mm pitch) |
| Temperature na Operasyon | -40 °C to +125 °C (industrial) | 0 °C to +85 °C (commercial, C5 grade) |
| Tindminan RoHS | Lead-free compliant | Compliant |
| Series | — | MAX II Device |
| Logic Elements (LEs) | — | 570 |
| Macrocells | — | 440 |
| Internal User Flash Memory | — | 8 Kbit |
| Global Clocks | — | 4 |
| Core Voltage (VCCINT) | — | 1.8 V (typical, internally regulated) |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage, per bank) |
| Maximum User I/O Pins | — | 116 |
| Propagation Delay (tPD) | — | 5.5 ns (typical, [DATA_NEEDED: exact speed grade]) |
| Maximum Frequency (fMAX) | — | 201.1 MHz |
| Uri ng Pagpapasok | — | Surface Mount |
| Programming Interface | — | IEEE 1149.1 JTAG (in-system programmable) |
| Configuration Storage | — | On-chip non-volatile flash |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI, LVDS, SSTL (per bank VCCIO) |
| Lead-Free | — | Yes |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |
| Design Software | — | Intel Quartus II (MAX II device support) |