EPM7096LC68-15 vs EPM7096LI68-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7096LC68-15 sa pamamagitan ng Altera at EPM7096LI68-15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM7096LC68-15 | EPM7096LI68-15 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Family | MAX 7000 | MAX 7000 (second-generation MAX architecture) |
| Macrocells | 96 | 96 |
| Logic Array Blocks (LABs) | 4 | 4 |
| User I/O Pins | 52 | 52 |
| Propagation Delay (tPD) | 15 ns | 15 ns |
| Supply Voltage (VCCINT/VCCIO) | 4.75 V to 5.25 V (5 V nominal) | — |
| Programmable Technology | EEPROM (second-generation MAX architecture) | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Logic Gates (typical) | 1800 gates | — |
| Memory Bits | Non-volatile configuration, 100 erase/program cycles per macrocell | — |
| Packhaging | PLCC-68 (LC68) | 68-pin PLCC (J-lead, QCCJ) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Surface Mount (J-lead) |
| Temperature na Operasyon | 0C to +70C (commercial) | — |
| Lead-Free / RoHS | Compliant per Altera product page | — |
| Programming Tool Support | Altera MAX+PLUS II, Quartus II; ByteBlaster / ByteBlasterMV | — |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Programmable Logic Type | — | EEPROM-based, in-system programmable (ISP) |
| Programming Interface | — | IEEE Std. 1149.1 JTAG |
| Boundary-Scan Test (BST) | — | Built-in JTAG BST circuitry |
| Output Option | — | Open-drain output option available |
| Operating Temperature Grade | — | Industrial (-40C to +85C) |
| Speed Grade | — | -15 (15 ns tPD) |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |
| Process Technology | — | CMOS EEPROM |