EPM7128AETI144-10N vs EPM7128AETC144-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128AETI144-10N sa pamamagitan ng Altera at EPM7128AETC144-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128AETI144-10N - MAX 7000A CPLD, 128 Macrocells, TQFP-144 | Altera
EPM7128AETI144-10N ObsoletePagsanggunian na paghahambing
| Parametro | EPM7128AETI144-10N | EPM7128AETC144-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 7000A | MAX 7000A |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Maximum User I/O Pins | 100 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) | — |
| Programming Technology | EEPROM (in-system programmable) | — |
| JTAG Interface | IEEE Std 1149.1 BST compliant | — |
| Packhaging | TQFP-144 (144-pin) | 144-pin TQFP (also referred to as LQFP-144) |
| Temperature na Operasyon | -40C to +85C (industrial) | 0C to +70C (Commercial) |
| Process Technology | 0.35 µm CMOS EEPROM | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | 3 | MSL 3 (per JEDEC J-STD-020) |
| Tindminan RoHS | Compliant | [DATA_NEEDED: rohs status from manufacturer] |
| Speed Grade | -10 (10 ns tPD) | — |
| Operating Frequency (fCNT) | [DATA_NEEDED: fCNT counter frequency] | — |
| Maximum User I/Os | — | 36 |
| Pin-to-pin Logic Delay (tPD) | — | 10 ns |
| Maximum Internal Counter Frequency | — | 98 MHz |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Voltage Tolerance | — | 2.5 V / 3.3 V / 5 V |
| Programming Interface | — | JTAG (IEEE Std. 1149.1) and ByteBlaster |
| Non-volatile Memory | — | EEPROM, instant-on |
| Global Clocks / Global OE | — | 2 / 2 |