EPM7128SLI84-10 vs EPM7128ELI84-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SLI84-10 sa pamamagitan ng Altera at EPM7128ELI84-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM7128ELI84-20 - 128-Macrocell CPLD, 20ns, 84-PLCC | Intel / Altera
EPM7128ELI84-20 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM7128SLI84-10 | EPM7128ELI84-20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | MAX 7000S | MAX 7000 (Classic / MAX 7000B/E) |
| Usable Gates | 2.5K | 2,500 |
| Macro Cells | 128 | 128 |
| User I/Os | 68 | — |
| Logic Array Blocks (LABs) | 8 | 8 |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | 5 V (4.75 V to 5.25 V for -20 speed grade) |
| Configuration Memory | EEPROM (in-system programmable) | — |
| Temperature na Operasyon | -40 °C to +85 °C (industrial) | -40 °C to +85 °C (Industrial) |
| Packhaging | 84-pin PLCC | 84-pin PLCC (J-Lead) |
| Uri ng Pagpapasok | Surface Mount / Socket | Surface Mount / Socketable (PLCC J-Lead) |
| Process Technology | CMOS | — |
| JTAG Support | Yes (IEEE 1149.1) | — |
| Tindminan RoHS | [DATA_NEEDED: lead-free variant is -10N suffix] | Compliant (lead-free PLCC variant) |
| Device Name | — | EPM7128E |
| Maximum User I/Os | — | 68 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Maximum Operating Frequency (fCNT) | — | 62.5 MHz |
| Programming Interface | — | JTAG (IEEE 1149.1) + ISP |
| Technology | — | EEPROM-based CMOS |