EPM7128SQC100-10 vs EPM7128SQC100-10F Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SQC100-10 sa pamamagitan ng Altera at EPM7128SQC100-10F sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128SQC100-10F - 128-Macrocell MAX 7000 CPLD, 10ns, 100-PQFP | Altera (Intel)
EPM7128SQC100-10F ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM7128SQC100-10 | EPM7128SQC100-10F |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | — |
| Logic Elements / Gates | 2,500 usable gates | — |
| Maximum User I/O | 84 | — |
| Logic Array Blocks (LABs) | 16 | 8 |
| Maximum Operating Frequency | 100 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Volte ng Pagbibigay | 5 V | — |
| Process Technology | 5V CMOS, EEPROM-based | CMOS EEPROM |
| Programmability | In-System Programmable (ISP) via JTAG | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Packhaging | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin PQFP (Plastic Quad Flat Pack) |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: rohs_status] | Compliant (F suffix variant) |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 2,500 |
| Macrocells | — | 128 |
| User I/Os | — | 84 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| Lead-Free (F suffix) | — | Yes (Pb-free finish) |