EPM7128SQC100-7N vs EPM7128SQC100-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SQC100-7N sa pamamagitan ng Intel at EPM7128SQC100-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
EPM7128SQC100-7N ObsoleteAltera
EPM7128SQC100-10N - MAX 7000 128-Macro-Cell CPLD, 10ns | Altera
EPM7128SQC100-10N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM7128SQC100-7N | EPM7128SQC100-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Family | MAX 7000S | MAX 7000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Program Memory Type | EEPROM | — |
| Number of Macrocells | 128 | — |
| Number of Logic Array Blocks | 8 | — |
| Number of Global Clocks | 2 | — |
| Product Terms per Macrocell | 32 | — |
| Usable Gates | 2,500 | 2,500 |
| System Gates | 5,000 (max) | — |
| Maximum User I/Os | 84 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Counter Speed | 175.4 MHz | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Operating Voltage (Core) | 5.0 V | — |
| I/O Standard Support | multiVolt (2.5V, 3.3V, 5.0V) | — |
| Packhaging | 100-pin PQFP (QFP-100) | 100-pin PQFP (BQFP) |
| Temperature na Operasyon | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Tindminan RoHS | Compliant (lead-free 'N' suffix) | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Security Bit | Programmable (one per device) | — |
| Macro Cells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 (16 macro cells each) |
| User I/O Pins | — | 84 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 5 V (4.75 V to 5.25 V) |
| I/O Voltage Tolerance | — | 3.3 V or 5 V (MultiVolt interface) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE Std 1149.1), 4-pin |
| Uri ng Pagpapasok | — | Surface Mount |
| Lead-Free / RoHS Status | — | Lead-free (N suffix) |
| Architecture Generation | — | Second-generation MAX |