EPM7128SQI100-15N vs EPM7128STI100-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SQI100-15N sa pamamagitan ng Intel at EPM7128STI100-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128STI100-10N - 128-Macrocell CPLD, 10ns, 100-pin TQFP | Altera
EPM7128STI100-10N ObsoletePagsanggunian na paghahambing
| Parametro | EPM7128SQI100-15N | EPM7128STI100-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Device Type | EE-PLD / CPLD | — |
| Macrocells | 128 | 128 |
| User I/Os | 80 | — |
| Usable Gates | 2,500 (typical) | 2,500 (up to 5,000 family max) |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Frequency (fCNT) | 76.9 MHz | — |
| Core Supply Voltage (VCCINT) | 4.5 V to 5.5 V | — |
| I/O Logic Levels | 3.3 V or 5 V (multi-volt I/O) | — |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| Packhaging | PQFP-100 (R-PQFP-G100) | 100-pin TQFP |
| Terminal Form | Gull Wing | — |
| Package Code | QFP | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | CMOS | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (JTAG IEEE 1149.1) |
| Non-volatile Configuration | EEPROM (instant-on) | — |
| Tindminan RoHS | Lead-free (N suffix) | [DATA_NEEDED: RoHS status] |
| Architecture | — | CMOS EEPROM-based CPLD |
| Logic Array Blocks (LABs) | — | 8 |
| Maximum User I/O | — | 84 |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 175.4 MHz |
| Supply Voltage (VCC) | — | 5 V |
| JTAG Boundary-Scan | — | Yes (BST) |
| Temperature na Operasyon | — | -40C to +85C (Industrial) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Open-Drain I/O Option | — | Available (per MAX 7000A feature set) |