EPM7160ELC84-20 vs EPM7128ELC84-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7160ELC84-20 sa pamamagitan ng Intel at EPM7128ELC84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM7160ELC84-20 | EPM7128ELC84-20 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 7000 | — |
| Macrocells | 160 | — |
| Logic Array Blocks | 4 | — |
| Usable Gates | 3,200 | — |
| User I/O Pins | 64 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5.0 V | 5 V |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Programming Interface | IEEE 1149.1 JTAG (ISP) | — |
| In-System Programmable | Yes (5.0-V ISP) | — |
| Packhaging | PLCC-84 (windowed ceramic carrier not applicable - plastic) | — |
| Technology | CMOS EEPROM | CMOS, EEPROM-based (non-volatile) |
| Architecture | Second-generation MAX | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance per specific part marking] | Contains lead (pre-RoHS, SnPb finish) |
| Global Clock Inputs | 4 | — |
| Logic Element Type | EEPROM-based macrocell | — |
| Series | — | MAX 7000 |
| Device Family | — | EPM7128 (CPLD) |
| Number of Macrocells | — | 128 |
| Number of Usable Gates | — | 2500 |
| Number of User I/Os | — | 68 |
| Number of Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Frequency (fCNT) | — | 62.5 MHz |
| Supply Voltage Tolerance | — | 4.75 V to 5.25 V |
| Programmable Interface | — | IEEE Std. 1149.1 (JTAG) |
| Package Type | — | PLCC-84 (J-Lead, J-bend) |
| Temperature na Operasyon | — | 0C to +70C (commercial) |