EPM7256AEFC100-7 vs EPM7256AETC100-5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256AEFC100-7 sa pamamagitan ng Intel at EPM7256AETC100-5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM7256AEFC100-7 - 256-Macrocell MAX 7000A CPLD, 100-FBGA | Intel
EPM7256AEFC100-7 ✓ NakahandaAltera
EPM7256AETC100-5N - 256-Macro MAX 7000A CPLD, 5ns TQFP-100
EPM7256AETC100-5N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM7256AEFC100-7 | EPM7256AETC100-5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Huling Pagbili |
| Family | MAX 7000A | MAX 7000A |
| Macro Cells | 256 | 256 |
| Usable Gates | 5,000 | 5000 (range 600 to 10000) |
| Logic Array Blocks | 16 | — |
| User I/Os | 84 | 84 |
| Packhaging | 100-pin FBGA (11x11 mm) | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Bilang ng Pin | 100 | — |
| Supply Voltage - VCCINT | 3.0 V to 3.6 V | — |
| Supply Voltage - VCCIO | 2.5 V, 3.3 V, or 5 V (MultiVolt) | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Internal Toggle Rate | 250 MHz | — |
| Maximum Operating Frequency | 126.6 MHz | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Uri ng Pagpapasok | Surface Mount (FBGA) | Surface Mount |
| Temperature na Operasyon | 0C to +90C (commercial) | 0C to +70C (Commercial) |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | Compliant (lead-free) |
| Level ng MSL | [DATA_NEEDED: msl level] | 3 (168 hours) |
| Series | — | MAX 7000AE |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 16 |
| Pin-to-Pin Delay (tPD) | — | 5.0 ns |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| MultiVolt I/O Support | — | 2.5 V / 3.3 V / 5.0 V |
| Program Memory | — | Internal EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Process Technology | — | CMOS, EEPROM-based |
| Security Bit | — | Programmable |