EPM7256AEFC100-7 vs EPM7256AETI100-7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256AEFC100-7 sa pamamagitan ng Intel at EPM7256AETI100-7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM7256AEFC100-7 - 256-Macrocell MAX 7000A CPLD, 100-FBGA | Intel
EPM7256AEFC100-7 ✓ NakahandaIntel
EPM7256AETI100-7N - 256-MacroCell MAX 7000A CPLD, 100TQFP | Intel
EPM7256AETI100-7N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM7256AEFC100-7 | EPM7256AETI100-7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Huling Pagbili |
| Family | MAX 7000A | MAX 7000A |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 | 5,000 |
| Logic Array Blocks | 16 | — |
| User I/Os | 84 | — |
| Packhaging | 100-pin FBGA (11x11 mm) | 100-pin TQFP (TQ100, 14x14 mm, 0.5 mm pitch) |
| Bilang ng Pin | 100 | — |
| Supply Voltage - VCCINT | 3.0 V to 3.6 V | — |
| Supply Voltage - VCCIO | 2.5 V, 3.3 V, or 5 V (MultiVolt) | — |
| Propagation Delay (tPD) | 7.5 ns | 7.5 ns |
| Internal Toggle Rate | 250 MHz | — |
| Maximum Operating Frequency | 126.6 MHz | 126.6 MHz |
| Programmable Type | In-System Programmable (EEPROM) | — |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Uri ng Pagpapasok | Surface Mount (FBGA) | Surface Mount |
| Temperature na Operasyon | 0C to +90C (commercial) | -40C to +85C (Industrial) |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | Compliant |
| Level ng MSL | [DATA_NEEDED: msl level] | 3 (168 hours) |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macrocells | — | 256 |
| Maximum User I/O | — | 84 |
| Logic Elements / Blocks | — | 16 Logic Array Blocks |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V |
| Technology | — | CMOS, EEPROM-based configuration |
| Programmability | — | In-system programmable via JTAG (IEEE 1149.1) |