EPM7256SQC208-7 vs EPM7256SQI208-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256SQC208-7 sa pamamagitan ng Altera at EPM7256SQI208-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM7256SQC208-7 | EPM7256SQI208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Device Family | MAX 7000S (EPM7256S) | MAX 7000 (EPM7256) |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | 5000 |
| User I/O Pins | 164 | — |
| Propagation Delay (tPD) | 7.5 ns | 10 ns |
| Maximum Operating Frequency (fMAX) | 128.2 MHz | — |
| Supply Voltage (VCC) | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Packhaging | 208-pin PQFP (28 x 28 mm, 0.5 mm pitch) | 208-pin PQFP (QFP208) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Hanay ng Temperature na Operasyon | Commercial (0C to +70C) | -40 C to +85 C (Industrial) |
| Minimum DC Input Voltage | -0.5 V | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns | — |
| Speed Grade | -7 (7.5 ns) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Logic Levels | 5.0 V CMOS/TTL compatible | — |
| Logic Array Blocks | — | 16 |
| Maximum User I/O Pins | — | 164 |
| Supply Voltage Range | — | 4.5 V to 5.5 V |
| Technology | — | CMOS EEPROM |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmable | — | Yes (IEEE 1149.1 JTAG) |
| Package Body Material | — | Plastic/Epoxy |
| Terminal Form | — | Gull Wing |
| JESD-30 Package Code | — | S-PQFP-G208 |
| JESD-609 Terminal Finish Code | — | E3 |