EPM9320ALC84-20 vs EPM9320ALC84-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ALC84-20 sa pamamagitan ng Altera at EPM9320ALC84-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320ALC84-20 | EPM9320ALC84-10 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/Os | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | 10 ns |
| Packhaging | PLCC-84 | 84-pin PLCC (J-Lead) |
| Process Technology | 0.5 µm CMOS EEPROM | — |
| Volte ng Pagbibigay | 5.0 V | — |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| Temperature na Operasyon | [DATA_NEEDED: commercial or industrial grade] | [DATA_NEEDED: commercial/industrial grade] |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Surface Mount / Through-Hole (PLCC socket) |
| Configuration Memory | Non-volatile EEPROM | — |
| Boundary Scan | JTAG IEEE 1149.1 | — |
| Design Software | MAX+PLUS II / Quartus II (legacy) | — |
| Tindminan RoHS | [DATA_NEEDED: per Altera datasheet] | [DATA_NEEDED] |
| Device | — | EPM9320 |
| Maximum User I/O Pins | — | 52 |
| Dedicated Inputs | — | 16 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Supply Voltage (VCCINT) | — | 5.0 V |
| In-System Programmability | — | 5.0 V ISP via IEEE 1149.1 JTAG |
| Technology | — | CMOS EEPROM-based, third-generation MAX |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| Non-Volatile Configuration | — | Yes (EEPROM cell, powers up in known state) |
| Architecture | — | MAX (Multiple Array MatriX) with FastTrack Interconnect |