EPM9320ARC208-10 vs EPM9320RC208-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ARC208-10 sa pamamagitan ng Altera at EPM9320RC208-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320ARC208-10 | EPM9320RC208-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Device Family | MAX 9000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | 6,000 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency | 144.9 MHz | — |
| Volte ng Pagbibigay | 5.0 V | — |
| Logic Blocks (LABs) | 16 | — |
| Programmability | EEPROM, in-system programmable via JTAG | — |
| JTAG Support | IEEE Std. 1149.1 compliant | — |
| Speed/Power Optimization | Per-macrocell programmable, 50% power mode available | — |
| Packhaging | RQFP-208 (Power Quad Flat Pack) | 208-RQFP, exposed pad (208-BFQFP) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0 °C to 70 °C (commercial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 20 |
| Maximum I/O Pins | — | 132 |
| Propagation Delay (tPD max) | — | 20 ns |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V |
| Programming Technology | — | EEPROM, in-system programmable (ISP) |
| Boundary-Scan Interface | — | IEEE Std. 1149.1 (JTAG) |
| Architecture | — | Multiple Array Matrix (MAX), 3rd generation |
| Process Technology | — | CMOS, 5.0 V EEPROM |
| Reprogrammability | — | Yes, unlimited ISP cycles |