EPM9320RC208-10 vs EPM9320RC208-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320RC208-10 sa pamamagitan ng Altera at EPM9320RC208-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320RC208-10 | EPM9320RC208-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | 20 |
| Packhaging | 208-pin RQFP (RC) | 208-RQFP, exposed pad (208-BFQFP) |
| Temperature na Operasyon | Commercial (0C to +70C) - 'C' suffix | 0 °C to 70 °C (commercial) |
| Volte ng Pagbibigay | 5 V | — |
| Speed Grade | -10 | — |
| Programming Interface | JTAG (ByteBlaster/BitBlaster) | — |
| Non-volatile Configuration | Yes (EPROM/EEPROM based) | — |
| Design Tool Support | MAX+PLUS II, Quartus (legacy) | — |
| Tindminan RoHS | ROHS3 Compliant (per fpgalink listing) | — |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 (168 Hours) | — |
| Lead Time | 1-7 days (per fpgalink listing) | — |
| Maximum I/O Pins | — | 132 |
| Propagation Delay (tPD max) | — | 20 ns |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V |
| Programming Technology | — | EEPROM, in-system programmable (ISP) |
| Boundary-Scan Interface | — | IEEE Std. 1149.1 (JTAG) |
| Uri ng Pagpapasok | — | Surface Mount |
| Architecture | — | Multiple Array Matrix (MAX), 3rd generation |
| Process Technology | — | CMOS, 5.0 V EEPROM |
| Reprogrammability | — | Yes, unlimited ISP cycles |