EPM9320RC208-20N vs EPM9320ARC208-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320RC208-20N sa pamamagitan ng Altera at EPM9320ARC208-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320RC208-20N | EPM9320ARC208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 9000 | — |
| Logic Type | Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 6,000 | — |
| Macro Cells | 320 | 320 |
| Logic Array Blocks | 20 | — |
| Maximum Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Volte ng Pagbibigay | 5.0 V | — |
| Configuration Memory | EEPROM (non-volatile) | Non-volatile EEPROM |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| User I/O Pins | 168 | 168 |
| Packhaging | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (BFQFP with exposed pad) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant (lead-free 'N' suffix) |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 6,000 gates |
| Logic Array Blocks (LABs) | — | 16 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency | — | 144.9 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Dedicated Input Pins | — | 12 |
| Programming Interface | — | IEEE Std. 1149.1 JTAG |