EPM9320RI208-20C vs EPM9320RI208-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320RI208-20C sa pamamagitan ng Altera at EPM9320RI208-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM9320RI208-10N EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N ✓ Nakahanda

Pagsanggunian na paghahambing

Parametro EPM9320RI208-20C EPM9320RI208-10N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Aktibo
Family MAX 9000 MAX 9000
Device Type EE PLD / CPLD Complex Programmable Logic Device (CPLD)
Logic Elements / Macrocells 320 —
Usable Gates 6,000 6,000
Number of Flip-Flops 484 —
Logic Array Blocks (LABs) 16 20
Maximum Internal Clock Frequency 100 MHz —
Pin-to-Pin Propagation Delay (tPD) 20 ns 10 ns
Supply Voltage (VCCINT/VCCIO) 5.0 V —
I/O Voltage Tolerance 3.3 V or 5.0 V —
Programmable Interface JTAG (IEEE Std. 1149.1) BST —
In-System Programmability Yes (5.0 V ISP via JTAG) Yes (JTAG/ISP)
Technology CMOS EEPROM —
Packhaging 208-pin RQFP (Plastic Quad Flat Pack) 208-pin RQFP (PowerQuad II)
Operating Temperature (Industrial) -40C to +85C —
Uri ng Pagpapasok Surface Mount Surface Mount
Lead-Free / RoHS Information not confirmed from verified data [DATA_NEEDED: RoHS status] —
Macro Cells — 320
Maximum System Clock Frequency — 100 MHz
Volte ng Pagbibigay — 5 V
I/O Voltage — 5 V
User I/O Pins — 160
Configuration Memory — EEPROM (non-volatile)
Hanay ng Temperature na Operasyon — -40C to +85C (industrial)
Tindminan RoHS — Compliant (N suffix = lead-free)
Lead Finish — Lead-free (matte tin)
Level ng MSL — [DATA_NEEDED: MSL level]

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita