EPM9560GC280-20N vs EPM9560ELI84-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560GC280-20N sa pamamagitan ng Altera at EPM9560ELI84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM9560ELI84-20 - MAX 9000 6k-Gate EPLD, 84-Pin PLCC | Intel / Altera
EPM9560ELI84-20 ObsoletePagsanggunian na paghahambing
| Parametro | EPM9560GC280-20N | EPM9560ELI84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | Multiple Array MatriX (MAX) - EEPROM-based |
| Technology | CMOS EEPROM-based | — |
| Usable Gates | 6,000 to 12,000 | 6,000 |
| Macrocells | 560 | 560 |
| User I/O Pins | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5.0 V |
| I/O Voltage | 3.3 V or 5 V (configurable) | — |
| In-System Programmability | Yes (5.0-V ISP via IEEE 1149.1 JTAG) | 5.0 V ISP via IEEE 1149.1 JTAG |
| Packhaging | 280-pin CPGA (Ceramic Pin Grid Array) | 84-pin PLCC |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| PCI Compliance | Yes | — |
| Temperature na Operasyon | [DATA_NEEDED: industrial/commercial grade] | -40C to +85C (industrial) |
| Tindminan RoHS | [DATA_NEEDED] | [DATA_NEEDED: RoHS status] |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O | — | 212 (package-dependent) |
| Flip-Flops | — | 212 |
| Pin-to-Pin Propagation Delay | — | 20 ns |
| Speed Grade | — | -20 |
| I/O Standards | — | 5.0 V, 3.3 V, 2.5 V (multiVolt I/O) |
| Uri ng Pagpapasok | — | Through-Hole / Socket |
| Process Technology | — | CMOS EEPROM |