EPM9560RC208-10N vs EPM9560RC208-15C Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-10N sa pamamagitan ng Intel at EPM9560RC208-15C sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Intel
EPM9560RC208-10N EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPM9560RC208-10N EPM9560RC208-15C
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family MAX 9000 MAX 9000
Device EPM9560 —
Macro Cells 560 —
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 16 —
User I/O Pins 153 149
Pin-to-Pin Delay (tPD1) 10 ns —
Supply Voltage (VCCINT) 5.0 V —
I/O Bank Voltage (VCCIO) 5.0 V —
Packhaging 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP
Uri ng Pagpapasok Surface Mount Surface Mount
Process Technology CMOS EEPROM —
Programmability In-system via IEEE 1149.1 JTAG —
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Type — EEPROM-based CPLD (EPLD)
Macrocells — 560
Propagation Delay (tPD) — 15 ns
Maximum Counter Frequency — 117.6 MHz
Supply Voltage Range — 4.75 V to 5.25 V
Nominal Supply Voltage — 5.0 V
I/O Voltage Compatibility — 3.3 V or 5 V
Configuration Memory — EEPROM (non-volatile)
In-System Programmability — Yes, via IEEE Std. 1149.1 JTAG
Hanay ng Temperature na Operasyon — 0C to +70C (commercial)
Speed Grade — -15 (15 ns)
Logic Architecture — Multiple Array MatriX (MAX) third generation

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