EPM9560RC208-14 vs EPM9560RC208-12 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-14 sa pamamagitan ng Altera at EPM9560RC208-12 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC208-14 | EPM9560RC208-12 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EEPROM-based CPLD |
| Usable Gates | 12,000 | 12000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 149 | — |
| Maximum Operating Frequency | 117.6 MHz | — |
| Pin-to-Pin Propagation Delay | 14 ns | — |
| Volte ng Pagbibigay | 5 V | — |
| I/O Voltage Support | 3.3 V / 5 V | — |
| Program Memory Type | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG, IEEE 1149.1) | — |
| Packhaging | 208-pin RQFP (PQFP) | 208-pin RQFP (S-PQFP-G208) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | 0.35 µm CMOS EEPROM | — |
| Tindminan RoHS | Non-compliant (legacy part) | [DATA_NEEDED: RoHS status] |
| Flip-Flops | — | 772 |
| User I/O Lines | — | 153 |
| Propagation Delay (tPD) | — | 12 ns |
| Maksimum na Taktiko ng Oras | — | 125 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Terminal Pitch | — | 0.50 mm |
| Temperature na Operasyon | — | 0C to +70C (commercial) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Logic Array Blocks | — | 20 |
| Speed Grade | — | -12 (12 ns) |