EPM9560RC208-17 vs EPM9560RC208-19 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-17 sa pamamagitan ng Altera at EPM9560RC208-19 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC208-17 | EPM9560RC208-19 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | — |
| Product Type | CPLD (EPLD, in-system programmable) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | — |
| Logic Array Blocks (LABs) | 16 | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | 17 ns | — |
| Maximum Counter Frequency | 117.6 MHz | — |
| User I/O Pins | 212 | 149 |
| Supply Voltage (VCC) | 5 V | — |
| Packhaging | 208-pin RQFP (RC208) | RQFP-208 (208-pin PQFP) |
| Programming Technology | EEPROM (in-system programmable) | — |
| Program/Erase Cycles | 100 minimum | — |
| JTAG (IEEE 1149.1) Support | Yes | — |
| Architecture | Third-generation MAX (AND-OR PLA) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Device Family | — | MAX 9000 |
| Macrocells | — | 560 |
| Flip-Flops | — | 772 |
| Propagation Delay (tPD) | — | 19 ns |
| Maximum Frequency | — | [DATA_NEEDED: fMAX] |
| Supply Voltage (VCCINT) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V / 5 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Technology | — | CMOS EEPROM |
| JEDEC Package Code | — | S-PQFP-G208 |
| Temperature na Operasyon | — | [DATA_NEEDED: operating temperature grade] |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |