EPM9560RC208-19 vs EPM9560RC208-15N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-19 sa pamamagitan ng Altera at EPM9560RC208-15N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP
EPM9560RC208-15N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM9560RC208-19 | EPM9560RC208-15N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Device Family | MAX 9000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | 16 |
| Flip-Flops | 772 | — |
| User I/O Pins | 149 | — |
| Propagation Delay (tPD) | 19 ns | — |
| Maximum Frequency | [DATA_NEEDED: fMAX] | — |
| Supply Voltage (VCCINT) | 5.0 V | 5.0 V |
| I/O Voltage Tolerance | 3.3 V / 5 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Technology | CMOS EEPROM | — |
| Packhaging | RQFP-208 (208-pin PQFP) | 208-pin RQFP (Power Quad Flat Pack) |
| JEDEC Package Code | S-PQFP-G208 | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature grade] | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: check part marking suffix for lead-free/RoHS] |
| Series | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| User I/O | — | 212 (in 208-RQFP, see family datasheet) |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Internal Frequency | — | 117.6 MHz |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| Configuration Memory | — | CMOS EEPROM (non-volatile) |
| Operating Temperature (commercial) | — | 0C to +70C |
| Speed Grade | — | -15 (15 ns tPD) |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |