EPM9560RC208-3 vs EPM9560RC208-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-3 sa pamamagitan ng Altera at EPM9560RC208-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM9560RC208-3 EPM9560RC208-3 - 560 Macrocell MAX 9000 EPLD | Intel / Altera

EPM9560RC208-3 - 560 Macrocell MAX 9000 EPLD | Intel / Altera

EPM9560RC208-3 ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPM9560RC208-3 EPM9560RC208-20
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family MAX 9000 —
Device Type EPLD (Erasable Programmable Logic Device) —
Macrocells 560 560
Logic Array Blocks (LABs) 16 —
Usable Gates 12,000 12,000
Maximum Operating Frequency [DATA_NEEDED: f_MAX] —
Pin-to-Pin Delay (speed grade -3) approximately 3 ns (slowest grade) —
Speed Grade -3 —
Packhaging 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (28x28 mm)
I/O Voltage Tolerance 5V —
Process Technology 0.5 µm CMOS EPROM —
Programming Interface ByteBlaster / BitBlaster (JTAG-compatible) —
Temperature na Operasyon [DATA_NEEDED: industrial / commercial range] 0C to +70C (commercial)
Tindminan RoHS [DATA_NEEDED] [DATA_NEEDED: RoHS status]
Lifecycle Mature / Last-time-buy (per Altera PDN for selected MAX 9000 ordering codes) —
Device Family — MAX 9000 (EPM9560)
Logic Array Blocks — 35
User I/O Pins — 153
Pin-to-Pin Delay (tPD) — 20 ns
Maksimum na Taktiko ng Oras — 100 MHz
Volte ng Pagbibigay — 5.0 V
Configuration Technology — EEPROM (non-volatile)
In-System Programmability — Yes, via IEEE Std. 1149.1 JTAG
Uri ng Pagpapasok — Surface Mount
I/O Standards — 5.0 V TTL/CMOS compatible
Flip-Flops — 772
Level ng MSL — [DATA_NEEDED: MSL level]

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita