EPM9560RC208-7N vs EPM9560RC208-15C Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-7N sa pamamagitan ng Intel at EPM9560RC208-15C sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM9560RC208-7N - MAX 9000 EPLD, 208-Pin RQFP, 7ns | Intel (Altera)
EPM9560RC208-7N ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EPM9560RC208-7N | EPM9560RC208-15C |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device | EPM9560 | — |
| Logic Elements / Macrocells | [DATA_NEEDED: macrocell count] | — |
| Usable Gates | [DATA_NEEDED: usable gate count] | 12,000 |
| Propagation Delay (tPD) | 7 ns (speed grade -7) | 15 ns |
| Packhaging | RQFP-208 (Power Quad Flat Pack) | 208-pin RQFP |
| Bilang ng Pin | 208 | — |
| User I/O | [DATA_NEEDED: user I/O count] | — |
| Process Technology | 0.65 micron CMOS EEPROM | — |
| Programmability | In-system / EEPROM-based | — |
| Volte ng Pagbibigay | 5 V (VCC, typical for MAX 9000) | — |
| Temperature na Operasyon | [DATA_NEEDED: commercial or industrial grade] | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant (Pb-free, N suffix) | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes (N suffix) | — |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | — | EEPROM-based CPLD (EPLD) |
| Macrocells | — | 560 |
| User I/O Pins | — | 149 |
| Maximum Counter Frequency | — | 117.6 MHz |
| Supply Voltage Range | — | 4.75 V to 5.25 V |
| Nominal Supply Voltage | — | 5.0 V |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Hanay ng Temperature na Operasyon | — | 0C to +70C (commercial) |
| Speed Grade | — | -15 (15 ns) |
| Logic Architecture | — | Multiple Array MatriX (MAX) third generation |