EPM9560RC210-20 vs EPM9560RC208-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC210-20 sa pamamagitan ng Altera at EPM9560RC208-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM9560RC210-20 EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

EPM9560RC210-20 ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPM9560RC210-20 EPM9560RC208-20
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family MAX 9000 —
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 560 560
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 16 —
Packhaging RQFP-210 (Power Quad Flat Pack, 0.5mm pitch) 208-pin RQFP (28x28 mm)
Pin-to-Pin Delay (tPD) 20 ns 20 ns
Clock-to-Output (tCO) 12 ns —
Maximum User I/O [DATA_NEEDED: 212 I/O per datasheet, package-dependent] —
Volte ng Pagbibigay 5 V 5.0 V
Process Technology 0.65 um EEPROM —
In-System Programmability Yes (MAX+PLUS II flow) Yes, via IEEE Std. 1149.1 JTAG
Boundary-Scan (JTAG) IEEE Std 1149.1 compliant —
Temperature na Operasyon [DATA_NEEDED: commercial 0C to 70C typical; industrial variants exist] 0C to +70C (commercial)
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS RoHS3 Compliant (per supplier listing) [DATA_NEEDED: RoHS status]
Device Family — MAX 9000 (EPM9560)
Logic Array Blocks — 35
User I/O Pins — 153
Maksimum na Taktiko ng Oras — 100 MHz
Configuration Technology — EEPROM (non-volatile)
I/O Standards — 5.0 V TTL/CMOS compatible
Flip-Flops — 772
Level ng MSL — [DATA_NEEDED: MSL level]

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