EPM9560RC240-12 vs EPM9560RC240-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC240-12 sa pamamagitan ng Altera at EPM9560RC240-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC240-12 | EPM9560RC240-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 (EPM9560) | MAX 9000 |
| Device Type | EE PLD / CPLD | Complex Programmable Logic Device (CPLD) |
| Macrocells | 560 | — |
| Flip-Flops | 772 | — |
| User I/O Pins | 191 | 192 |
| Logic Array Blocks (LABs) | 20 | 12 |
| Maximum Propagation Delay (tPD) | 13.4 ns | — |
| Speed Grade | -12 (13.4 ns tPD) | — |
| Maximum Operating Frequency (estimated) | ~76 MHz registered | — |
| Core Supply Voltage (VCCINT) | 5 V | — |
| I/O Logic Levels | 3.3 V or 5 V (configurable) | — |
| Packhaging | PQFP-240 (RC240) 0.500 mm pitch, gull-wing | 240-pin RQFP (PowerQuad) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | Non-volatile EEPROM (instant-on) |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Process Technology | CMOS | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | ROHS3 Compliant |
| Usable Gates | — | 12,000 gates |
| Macro Cells | — | 560 |
| Maximum System Frequency | — | 144.9 MHz |
| Pin-to-Pin Propagation Delay | — | 10 ns |
| Volte ng Pagbibigay | — | 5 V |
| Technology | — | CMOS EEPROM |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | 3 (168 Hours) |
| Manufacturer Standard Lead Time | — | 1-7 Days (distributor stock) |