EPM9560RC30415 vs EPM9560RC304-15C Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC30415 sa pamamagitan ng Intel at EPM9560RC304-15C sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM9560RC304-15C - 560 Macro Cell MAX 9000 CPLD 117.6MHz 5V | Altera
EPM9560RC304-15C ObsoletePagsanggunian na paghahambing
| Parametro | EPM9560RC30415 | EPM9560RC304-15C |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX), EEPROM-based | Multiple Array MatriX (MAX), 3rd generation |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 (40 macro cells each) | 16 |
| User I/O Pins | 360 | — |
| Bilang ng Pin | 304 | — |
| Packhaging | 304-RQFP (Power Quad Flat Pack) | 304-pin RQFP |
| Speed Grade | -15 (15 ns pin-to-pin delay) | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Volte ng Pagbibigay | 5.0 V | 5.0 V |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (IEEE 1149.1 JTAG) |
| Technology | CMOS EEPROM | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| User I/O Pins (maximum) | — | 212 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Process Technology | — | CMOS EEPROM |
| Program/Erase Endurance | — | 100 cycles minimum |
| Temperature na Operasyon | — | 0 C to +70 C (Commercial) |