EPM9560RI208-20W vs EPM9560RI208-20N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI208-20W sa pamamagitan ng Intel at EPM9560RI208-20N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RI208-20W | EPM9560RI208-20N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 LABs of 40 macrocells each | — |
| User I/O Pins | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Speed Grade | -20 | — |
| Volte ng Pagbibigay | 5.0 V | 5.0 V |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes, via IEEE Std. 1149.1 JTAG |
| Programming Technology | CMOS EEPROM | — |
| Packhaging | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP |
| Temperature na Operasyon | -40C to +85C (Industrial) | Industrial (-40C to +85C) |
| Architecture | Third-generation Multiple Array MatriX (MAX) | — |
| Device Family | — | MAX 9000 |
| Pin-to-Pin Delay | — | 20 ns (-20 speed grade) |
| Counter Speed | — | 100 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| Uri ng Pagpapasok | — | Surface Mount |
| Development Tool | — | MAX+PLUS II |
| Design Entry | — | Schematic, VHDL, Verilog HDL, AHDL |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |
| Packaging | — | Tray |
| Logic Architecture | — | Third-generation MAX (Multiple Array MatriX) |
| Fabrication Process | — | Advanced CMOS |